Invention Grant
- Patent Title: Methods of forming interconnect structures using a vacuum environment
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Application No.: US15886190Application Date: 2018-02-01
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Publication No.: US10679891B2Publication Date: 2020-06-09
- Inventor: Chia-Ching Tsai , Yi-Wei Chiu , Hung Jui Chang , Li-Te Hsu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/768 ; H01L21/8238 ; H01L27/092 ; H01L29/78 ; H01L29/66 ; H01L23/532 ; H01L23/522
Abstract:
An interconnect structure and a method of forming are provided. The method includes forming an opening in a dielectric layer and an etch stop layer, wherein the opening extends only partially through the etch stop layer. The method also includes creating a vacuum environment around the device. After creating the vacuum environment around the device, the method includes etching through the etch stop layer to extend the opening and expose a first conductive feature. The method also includes forming a second conductive feature in the opening.
Public/Granted literature
- US20190006231A1 Interconnect Structure and Methods of Forming Public/Granted day:2019-01-03
Information query
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