Invention Grant
- Patent Title: Wafer scale testing and initialization of small die chips
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Application No.: US15722409Application Date: 2017-10-02
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Publication No.: US10679912B2Publication Date: 2020-06-09
- Inventor: Akihiro Horibe , Yasuteru Kohda , Seiji Munetoh , Chitra Subramanian , Kuniaki Sueoka
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L21/66 ; H01L21/77 ; H01L23/00

Abstract:
A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.
Public/Granted literature
- US20190103327A1 WAFER SCALE TESTING AND INITIALIZATION OF SMALL DIE CHIPS Public/Granted day:2019-04-04
Information query
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