An integrated circuit has a first gated diode with one or more diode fingers. Each diode finger has an elevated gate, an underlying p-type diffusion, and an underlying n-type diffusion. Each diffusion has a base region and an annular side region located between the base region and the elevated gate such that the diffusions have increased lateral surface areas that support greater current levels for the diode finger, which enables gated diodes to be implemented with fewer fingers and therefore less layout area than equivalent conventional gated diodes that do not have elevated gates. The first gated diode can be implemented with an analogous second gated diode to form ESD-protection circuitry for the integrated circuit.