Invention Grant
- Patent Title: Row orthogonality in LDPC rate compatible design
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Application No.: US15975440Application Date: 2018-05-09
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Publication No.: US10680646B2Publication Date: 2020-06-09
- Inventor: Thomas Richardson
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Patterson+ Sheridan, L.L.P. Qualcomm
- Main IPC: H03M13/11
- IPC: H03M13/11 ; H03M13/00 ; H04L1/00 ; H04L1/18

Abstract:
Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low-density parity check (LDPC) codes, for example, using a parity check matrix having full row-orthogonality. An exemplary method for performing low-density parity-check (LDPC) decoding includes receiving soft bits associated to an LDPC codeword and performing LDPC decoding of the soft bits using a parity check matrix, wherein each row of the parity check matrix corresponds to a lifted parity check of a lifted LDPC code, at least two columns of the parity check matrix correspond to punctured variable nodes of the lifted LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which the at least two punctured variable nodes are both connected.
Public/Granted literature
- US20190013827A1 ROW ORTHOGONALITY IN LDPC RATE COMPATIBLE DESIGN Public/Granted day:2019-01-10
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