Invention Grant
- Patent Title: Interconnect structure and method of forming same
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Application No.: US16154154Application Date: 2018-10-08
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Publication No.: US10682523B2Publication Date: 2020-06-16
- Inventor: Shu-Ting Tsai , Jeng-Shyan Lin , Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Feng-Chi Hung
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; A61N1/39 ; H01L25/00 ; H01L27/06 ; H01L27/146 ; H01L21/768 ; H01L23/532
Abstract:
A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.
Public/Granted literature
- US20190046806A1 Interconnect Structure and Method of Forming Same Public/Granted day:2019-02-14
Information query
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