Invention Grant
- Patent Title: Layout for integrated circuit and the integrated circuit
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Application No.: US16228530Application Date: 2018-12-20
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Publication No.: US10685162B2Publication Date: 2020-06-16
- Inventor: Cheok-Kei Lei , Yu-Chi Li , Chia-Wei Tseng , Zhe-Wei Jiang , Chi-Lin Liu , Jerry Chang-Jui Kao , Jung-Chan Yang , Chi-Yu Lu , Hui-Zhong Zhuang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, P.C., Intellectual Property Attorneys
- Agent Anthony King
- Main IPC: G06F30/392
- IPC: G06F30/392 ; G06F30/394 ; G06F30/398

Abstract:
A layout of an integrated circuit includes: a first layout device; a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein the second layout device is a redundant circuit in the integrated circuit; a conductive path disposed across the boundary of the first layout device and the second layout device; and a cut layer disposed on the conductive path and nearby the boundary for disconnecting the first layout device from the second layout device by cutting the conductive path into a first conductive portion and a second conductive portion according to a position of the cut layer; wherein the first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.
Public/Granted literature
- US20190121931A1 LAYOUT FOR INTEGRATED CIRCUIT AND THE INTEGRATED CIRCUIT Public/Granted day:2019-04-25
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