Invention Grant
- Patent Title: Computationally efficient nano-scale conductor resistance model
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Application No.: US15905719Application Date: 2018-02-26
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Publication No.: US10685163B2Publication Date: 2020-06-16
- Inventor: Karim El Sayed , Victor Moroz
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Warren S. Wolfeld; Andrew L. Dunlap
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F30/394 ; G06F30/20 ; G06F30/367 ; H01L23/522

Abstract:
Disclosed is technology for evaluating the performance of various conducting structures in an integrated circuit. A three-dimensional circuit representation of a circuit design is provided. The three-dimensional circuit representation includes a plurality of conducting structures including a first conducting structure which has a length L. A plurality of longitudinally adjacent volume elements is identified in the conducting structure. A width Wn and a height Hn are estimated for each volume element n in the conducting structure. Furthermore, the local resistivity ρn for each volume element n is estimated based on a function that is dependent upon the length L of the conducting structure and the width Wn and height Hn of the volume element n. The resistance of a conducting structure is estimated in dependence upon the resistivity ρn for each of the volume elements n in the plurality of volume elements in the conducting structure.
Public/Granted literature
- US20180253524A1 Computationally Efficient Nano-Scale Conductor Resistance Model Public/Granted day:2018-09-06
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