An operating method of the semiconductor memory device including a plurality of memory cells each having one of “n” number of program statuses as a target program status. The operating method includes performing a program operation to the memory cells according to one of first to third program mode set until a first condition is met; performing the program operation to the memory cells according to another one of first to third program mode set until a second condition is met; and performing the program operation to the memory cells according to a remaining one of first to third program mode set.