Invention Grant
- Patent Title: Method of semiconductor integrated circuit fabrication
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Application No.: US16173492Application Date: 2018-10-29
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Publication No.: US10685867B2Publication Date: 2020-06-16
- Inventor: De-Wei Yu , Tsu-Hsiu Perng , Ziwei Fang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/02 ; H01L29/06 ; H01L29/78 ; H01L29/66 ; H01L21/768 ; H01L21/285

Abstract:
A method of semiconductor device fabrication includes providing a substrate having a hardmask layer thereover. The hardmask layer is patterned to expose the substrate. The substrate is etched through the patterned hardmask layer to form a first fin element and a second fin element extending from the substrate. An isolation feature between the first and second fin elements is formed, where the isolation feature has a first etch rate in a first solution. A laser anneal process is performed to irradiate the isolation feature with a pulsed laser beam. A pulse duration of the pulsed laser beam is adjusted based on a height of the isolation feature. The isolation feature after performing the laser anneal process has a second etch rate less than the first etch rate in the first solution.
Public/Granted literature
- US20190067083A1 METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION Public/Granted day:2019-02-28
Information query
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