Invention Grant
- Patent Title: Liner and cap structures for reducing local interconnect vertical resistance without compromising reliability
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Application No.: US16133785Application Date: 2018-09-18
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Publication No.: US10685876B2Publication Date: 2020-06-16
- Inventor: Su Chen Fan , Hemanth Jagannathan , Raghuveer R. Patlolla , Cornelius Brown Peethala
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/532 ; H01L23/522

Abstract:
Embodiments of the invention are directed to an interconnect stack including a first dielectric layer, a first trench formed in the first dielectric layer, and a first liner deposited in the first trench, wherein the first liner defines a second trench. A first conductive material is in the second trench and deposited over the first dielectric layer and the first conductive material. A third trench extends through the second dielectric layer and is over the first conductive material. A bottom surface of the third trench includes at least a portion of the top surface of the first conductive material. A second liner is in the third trench, on sidewalls of the third trench, and also on the portion of the top surface of the first conductive material. The second liner functions as a cap region configured to counter electro-migration or surface migration of the first conductive material.
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