Electrical isolation between adjacent stripes of drain-select-level electrically conductive layers can be provided by forming a drain-select-level isolation structure between neighboring rows of memory stack structures. The drain-select-level isolation structure can partially cut through upper regions of the neighboring rows of memory stack structures. Vertical semiconductor channels of the neighboring rows of memory stack structures include a lower tubular segment and an upper semi-tubular segment that contact the drain-select-level isolation structure. Electrical current through drain select levels is limited to the semi-tubular segment of each vertical semiconductor channel. Alternatively, the drain-select-level isolation structure can be formed around the memory stack structures within the neighboring rows of memory stack structures. Ion implantation can be used to suppress conduction of electrical current through portions of vertical semiconductor channels that are proximal to the drain-select-level isolation structure.