Invention Grant
- Patent Title: Power gated lookup table circuitry
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Application No.: US15633322Application Date: 2017-06-26
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Publication No.: US10686446B2Publication Date: 2020-06-16
- Inventor: Bee Yee Ng , Hee Kong Phoon , Teik Hong Ooi , Guan Hoe Oh
- Applicant: Altera Corporation
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H03K19/17728
- IPC: H03K19/17728 ; H03K19/1776 ; H03K19/00 ; H03K19/173

Abstract:
A programmable integrated circuit with lookup table circuitry is provided. The lookup table (LUT) circuitry may be formed using multiplexers. A multiplexer in the lookup table circuitry may be implemented using only tristate inverting circuits. Each tristate inverting circuit may include a first set of n-channel and p-channel transistors that receive a static control bit from a memory element and a second set of n-channel and p-channel transistors that receive true and complementary versions of a user signal. The first and second sets of transistors may be coupled in series between a positive power supply terminal and a ground power supply terminal. A LUT multiplexer implemented in this way need not include separate transmission gates at the output of each tristate inverting circuit and may exhibit minimal subthreshold leakage.
Public/Granted literature
- US20170294914A1 POWER GATED LOOKUP TABLE CIRCUITRY Public/Granted day:2017-10-12
Information query
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