A latched comparator comprises a pre-amplifier stage with a positive input (Vin,p), a negative input (Vin,n); and a differential output (ΔVout) comprising a first output (Vout,1) and a second output (Vout,2), the pre-amplifier stage comprising a first cascode pair, comprising a first amplifying transistor (MN2) and a first cascode transistor (MN4) connected at a first cascode node, the first amplifying transistor (MN2) being controlled by the positive input (Vin,p) and the first cascode transistor (MN4) being connected, opposite to the first cascode node, to the first output (Vout,1); a second cascode pair, comprising a second amplifying transistor (MN3) and a second cascode transistor (MN5) connected at a second cascode node, the second amplifying transistor (MN3) being controlled by the negative input (Vin,n) and the second cascode transistor (MN5) being connected, opposite to the second cascode node, to the second output (Vout,2); a first gain-boosting transistor (MN6) connected between the first output (Vout,1) and the first cascode node; and a second gain-boosting transistor (MN7) connected between the second output (Vout,2) and the second cascode node, wherein the first gain-boosting transistor (MN6) and the second gain-boosting transistor (MN7) are cross-coupled, so that the first gain-boosting transistor (MN6) is controlled by the second output (Vout,2) and the second gain-boosting transistor (MN7) is controlled by the first output (Vout,2).