Invention Grant
- Patent Title: System and method for a hybrid current-mode and voltage-mode integrated circuit
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Application No.: US16436130Application Date: 2019-06-10
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Publication No.: US10691162B2Publication Date: 2020-06-23
- Inventor: Matthew Guthaus , Riadul Islam
- Applicant: The Regents of the University of California
- Applicant Address: US CA Oakland
- Assignee: The Regents of the University of California
- Current Assignee: The Regents of the University of California
- Current Assignee Address: US CA Oakland
- Agency: Venable LLP
- Agent Henry J. Daley; Ryan T. Ward
- Main IPC: G06F1/10
- IPC: G06F1/10 ; H03K5/1534 ; G06F30/392 ; G06F30/394 ; G06F30/396 ; G06F111/04

Abstract:
Systems and methods for a hybrid current-mode to voltage-mode integrated circuit. An example integrated circuit embodiment configured according to this disclosure can include: a clock circuit and a logic circuit operatively synchronized with said clock circuit, where the logic circuit has a plurality of sub-circuits. The clock circuit can include a current-mode network tree and a plurality of current-mode-to-voltage-mode converters, each current-mode-to-voltage-mode converter in the plurality of current-mode-to-voltage-mode converters being electrically connected to the current-mode network tree, and each current-mode-to-voltage-mode converter in the plurality of current-mode-to-voltage-mode converters being associated with a respective one of the plurality of sub-circuits. The clock circuit can also include a global current mode transmitter electrically connected to the current-mode network tree, where the global current mode transmitter provides a current-mode clock signal to each of the plurality of current-mode-to-voltage-mode converters.
Public/Granted literature
- US20190384349A1 SYSTEM AND METHOD FOR A HYBRID CURRENT-MODE AND VOLTAGE-MODE INTEGRATED CIRCUIT Public/Granted day:2019-12-19
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