Invention Grant
- Patent Title: High bandwidth connection between processor dies
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Application No.: US16284712Application Date: 2019-02-25
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Publication No.: US10691497B2Publication Date: 2020-06-23
- Inventor: Altug Koker , Abhishek R. Appu , Kiran C. Veernapu , Joydeep Ray , Balaji Vembu
- Applicant: INTEL CORPORATIOON
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06F9/50
- IPC: G06F9/50 ; G06T1/20

Abstract:
Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive a completion acknowledgment from the plurality of graphics processing units and in response to a determination that the workload is finished, to terminate one or more communication connections on the interconnect bridge. Other embodiments are also disclosed and claimed.
Public/Granted literature
- US20190266021A1 HIGH BANDWIDTH CONNECTION BETWEEN PROCESSOR DIES Public/Granted day:2019-08-29
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