Invention Grant
- Patent Title: Memory system for error test
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Application No.: US16025309Application Date: 2018-07-02
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Publication No.: US10692585B2Publication Date: 2020-06-23
- Inventor: Sung Jin Park , Jong Min Lee
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T GROUP LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@59ea62e1
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/44 ; G11C29/38 ; G11C29/12 ; G11C29/36 ; G11C29/46 ; G11C29/42

Abstract:
A memory system includes: a memory controller configured to control communication between a host and a memory device; and an error test device configured to store error operation codes for generating errors, wherein the error test device outputs the error operation codes to the memory controller under the control of the memory controller, and wherein the memory controller determines whether an error has been generated in any operation corresponding to any of the error operation codes, and, when it is determined that an error has been generated, the memory controller stores one or more error requests corresponding to the generated error.
Public/Granted literature
- US20190164625A1 MEMORY SYSTEM FOR ERROR TEST Public/Granted day:2019-05-30
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