An ESD protection device structure compatible with CMOS process is disclosed. In the ESD protection device structure, a power source I/O unit or a signal I/O unit of an I/O circuit is electrically connected to an electrostatic discharge clamp circuit including multiple low-voltage PMOS structure are formed in the P-type substrate and connected in series. Source and gate on low voltage N-type well of first low-voltage PMOS structure are electrically connected to a high-voltage power terminal pad through a first power line, or electrically connected to a signal transmission terminal pad through a signal transmission line, and drain of final low-voltage PMOS structure is electrically connected to a high voltage ground terminal pad through second power line. The ESD protection device structure using the serially-connected low-voltage PMOS structures only, can use the circuit layout area more efficiently and provide high ESD tolerance.