Invention Grant
- Patent Title: Protection of high-K dielectric during reliability anneal on nanosheet structures
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Application No.: US16282607Application Date: 2019-02-22
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Publication No.: US10692985B2Publication Date: 2020-06-23
- Inventor: Nicolas J. Loubet , Sanjay C. Mehta , Vijay Narayanan , Muthumanickam Sankarapandian
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L29/423 ; H01L29/06 ; H01L29/786 ; H01L29/49 ; H01L29/51 ; H01L21/28 ; H01L29/66 ; H01L29/10 ; H01L29/775 ; B82Y10/00

Abstract:
A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrate forming an interfacial layer over the nanosheets depositing a high-k dielectric layer conformally on the interfacial layer. The method also includes depositing a layer of silicon nitride (SiN) above the high-k dielectric layer and performing reliability anneal after depositing the layer of SiN to crystalize the high-k dielectric layer.
Public/Granted literature
- US20190189766A1 PROTECTION OF HIGH-K DIELECTRIC DURING RELIABILITY ANNEAL ON NANOSHEET STRUCTURES Public/Granted day:2019-06-20
Information query
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