A half-bridge driver circuit is configured to generate drive signals based on control signals. A processing circuit is configured to generate high side and low side control signals based on a control signal. An edge detector is configured to generate first and second signals in response to rising and falling edges in the control signal. A state machine transitions between states in response to the first and second signals, and is configured to sequentially, in response to the first signal, set the high side and low side control signals low; in response to the second signal, set the high side control signal high and the low side control signal low; in response to the first signal, set the high side and low side control signals low; and in response to the second signal, set the high side control signal low and the low side control signal high.