Invention Grant
- Patent Title: Method for optimized wafer process simulation
-
Application No.: US15427496Application Date: 2017-02-08
-
Publication No.: US10698320B2Publication Date: 2020-06-30
- Inventor: Ru-Gun Liu , Shih-Ming Chang , Shuo-Yen Chou , Zengqin Zhao , Chien Wen Lai
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: G03F7/20
- IPC: G03F7/20 ; G03F9/00 ; H01L23/544

Abstract:
A method includes establishing a simulation process for simulating fabrication of a structure on a wafer. The simulation process includes multiple simulation steps for simulating multiple wafer fabrication steps respectively, and further includes a step of testing the structure that produces a result representing quality of the structure. Each of the simulation steps has a respective adjustable process parameter. The method further includes specifying a respective workable range for each process parameter and running the simulation process in iterations using a wafer process simulator until the result becomes optimal. During the running of the simulation process, every two consecutive iterations either adjust two different process parameters within their workable ranges or adjust a same process parameter at opposite directions within its workable range.
Public/Granted literature
- US20180165388A1 Method for Optimized Wafer Process Simulation Public/Granted day:2018-06-14
Information query
IPC分类: