Invention Grant
- Patent Title: Hardware accelerator for compressed RNN on FPGA
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Application No.: US15390563Application Date: 2016-12-26
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Publication No.: US10698657B2Publication Date: 2020-06-30
- Inventor: Junlong Kang , Song Han , Yi Shan
- Applicant: BEIJING DEEPHI INTELLIGENCE TECHNOLOGY CO., LTD.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agency: IPro, PLLC
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@34a4dca7 com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@3802148f com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@1c8d369f com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@53616c54
- Main IPC: G06F7/501
- IPC: G06F7/501 ; G06F7/523 ; G06F7/544 ; G06N3/04 ; G06N3/063
Abstract:
The present invention relates to recurrent neural network. In particular, the present invention relates to how to implement and accelerate a recurrent neural network based on an embedded FPGA. Specifically, it proposes an overall design processing method of matrix decoding, matrix-vector multiplication, vector accumulation and activation function. In another aspect, the present invention proposes an overall hardware design to implement and accelerate the above process.
Public/Granted literature
- US20180046897A1 HARDWARE ACCELERATOR FOR COMPRESSED RNN ON FPGA Public/Granted day:2018-02-15
Information query
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