Invention Grant
- Patent Title: Method and system for profiling performance of a system on chip
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Application No.: US15414776Application Date: 2017-01-25
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Publication No.: US10698805B1Publication Date: 2020-06-30
- Inventor: Meir Ovadia
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: CADENCE DESIGN SYSTEMS, INC.
- Current Assignee: CADENCE DESIGN SYSTEMS, INC.
- Current Assignee Address: US CA San Jose
- Agency: Pearl Cohen Zedek Latzer Baratz LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F11/30 ; G06F9/44 ; G06F11/36 ; G06F11/07 ; G06F11/273

Abstract:
A method for debugging a system on chip (SoC) under test, may include automatically inserting commands in a test code for testing the SoC for invoking printing of messages of data, each message of the messages including start time, end time of each executed action of a plurality of actions, the executed action to be invoked by the test code when testing the SoC, the data further including identity of a processing component of a plurality of processing components of the SoC, on which the executed action was executed; recording the data of the invoked printed messages during testing of the test code on the SoC; and displaying, via a graphical user interface, one or a plurality of graphical representations, each of said graphical representations relating to a period of activity of one of the plurality of processing components over time, based on the recorded data.
Information query