A system for writing to a cache line, the system including: at least one processor; and at least one memory having stored thereon instructions that, when executed by the at least one processor, controls the at least one processor to: pre-emptively invalidate a cache line at a reader device; receive, from the reader device, a read request for the invalidated cache line; delay a response to the read request; and after the delay, output for transmission a response to the read request to the reader device.