Invention Grant
- Patent Title: Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput
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Application No.: US15881515Application Date: 2018-01-26
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Publication No.: US10698833B2Publication Date: 2020-06-30
- Inventor: Karthikeyan Avudaiyappan , Sourabh Alurkar
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G06F12/0895

Abstract:
A method for supporting a plurality of requests for access to a data cache memory (“cache”) is disclosed. The method comprises accessing a first set of requests to access the cache, wherein the cache comprises a plurality of blocks. Further, responsive to the first set of requests to access the cache, the method comprises accessing a tag memory that maintains a plurality of copies of tags for each entry in the cache and identifying tags that correspond to individual requests of the first set. The method also comprises performing arbitration in a same clock cycle as the accessing and identifying of tags, wherein the arbitration comprises: (a) identifying a second set of requests to access the cache from the first set, wherein the second set accesses a same block within the cache; and (b) selecting each request from the second set to receive data from the same block.
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Information query