Disclosed is a DDR SDRAM physical layer interface circuit including: a multiphase clock generator generating a plurality of clocks including a reference clock, a first clock, a second clock and a third clock; a frequency dividing circuit generating a PHY clock according to the first clock; a clock output path outputting the reference clock to a storage circuit; a first output circuit outputting a first output signal to the storage circuit according to a first input signal of a memory controller, the first clock and the PHY clock; a second output circuit outputting a second output signal to the storage circuit according to a second input signal of the memory controller, the second clock and the PHY clock; and a third output circuit outputting a third output signal to the storage circuit according to a third input signal of the memory controller, the third clock and the PHY clock.