A semiconductor device includes a delay circuit, a read control circuit, and a register control circuit. The delay circuit generates a read control signal by delaying a column control pulse and an internal column control pulse including pulses sequentially generated based on an operation mode signal during a read operation and generates a register control signal by delaying the column control pulse including a pulse generated based on a mode register enablement signal during a mode register read operation. The read control circuit generates an input/output (I/O) control signal from a bank address signal when the read control signal is enabled. The register control circuit outputs a mode information signal as a mode output information signal when the register control signal is enabled.