Methods, systems, and devices for mitigating line-to-line capacitive coupling in a memory die are described. A device may include multiple drivers configured to both drive latched data and conduct read and write operations. For example, a memory device may contain two or more memory arrays independently coupled to two drivers via two data lines. One data line may be driven strongly to shield a corresponding memory array from effects associated with data line capacitive coupling. An opposing data line may be driven with data pertaining to an access operation of the memory array to which it is coupled. The opposing data line may be driven concurrently or within a small time difference of the other data line.