Invention Grant
- Patent Title: Reduced resistance source and drain extensions in vertical field effect transistors
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Application No.: US16276118Application Date: 2019-02-14
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Publication No.: US10700195B2Publication Date: 2020-06-30
- Inventor: Peng Xu , Chun W. Yeung , Chen Zhang
- Applicant: TESSERA, INC.
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/02 ; H01L29/66 ; H01L21/311 ; H01L29/08
Abstract:
Semiconductor devices and methods of forming the same include forming first charged spacers on sidewalls of a semiconductor fin. A gate stack on the fin is formed over the first charged spacers. Second charged spacers are formed on sidewalls of the fin above the gate stack. The fin is recessed to a height below a top level of the second charged spacers.
Public/Granted literature
- US20190181263A1 REDUCED RESISTANCE SOURCE AND DRAIN EXTENSIONS IN VERTICAL FIELD EFFECT TRANSISTORS Public/Granted day:2019-06-13
Information query
IPC分类:
