Invention Grant
- Patent Title: Semiconductor devices and related methods
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Application No.: US16200969Application Date: 2018-11-27
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Publication No.: US10700279B2Publication Date: 2020-06-30
- Inventor: Jun Liu , Kunal R. Parekh
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L43/02 ; H01L27/24 ; H01L21/033 ; H01L21/768 ; H01L43/08 ; H01L43/12

Abstract:
Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.
Public/Granted literature
- US20190103556A1 SEMICONDUCTOR DEVICES AND RELATED METHODS Public/Granted day:2019-04-04
Information query
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