Invention Grant
- Patent Title: Mixer bias circuit
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Application No.: US16729548Application Date: 2019-12-30
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Publication No.: US10700641B1Publication Date: 2020-06-30
- Inventor: Ka-Un Chan , Rong-Fu Yeh , Chao-Huang Wu
- Applicant: REALTEK SEMICONDUCTOR CORPORATION
- Applicant Address: TW Hsinchu
- Assignee: REALTEK SEMICONDUCTOR CORPORATION
- Current Assignee: REALTEK SEMICONDUCTOR CORPORATION
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, PC
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@6b1f1818
- Main IPC: H04B1/18
- IPC: H04B1/18 ; H03D7/12 ; H04B1/16 ; H03F3/45

Abstract:
The present invention discloses a mixer bias circuit including a first reference voltage generation circuit, an amplifier, a first transistor array, a first switch array, a second reference voltage generation circuit, a second transistor array, a second switch array, a first resistive component, and a second resistive component. The mixer bias circuit provides multiple bias voltages by dynamically tracking the common mode voltage of a trans-impedance amplifier (TIA) and compensates for imbalance and mismatch effects by asymmetrically trimming the bias voltages to improve the second-order intercept point of a radio frequency (RF) receiver front-end (RXFE).
Public/Granted literature
- US20200212845A1 Mixer bias circuit Public/Granted day:2020-07-02
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