CMOS quarter-rate multiplexer for high-speed serial links
Abstract:
Various aspects provide for a multiplexer for high-speed serial links. For example, a system can include a first stage data path multiplexer circuit and a second stage data path multiplexer circuit. The first stage data path multiplexer circuit comprises a first inverter circuit to select a first data signal from a set of data signals and a second inverter circuit to select a second data signal from the set of data signals. The first inverter circuit comprises a first set of inverters and a first set of transmission gates. The second inverter circuit comprises a second set of inverters and a second set of transmission gates. The second stage data path multiplexer circuit is configured as a third inverter circuit to select the first data signal or the second data signal as an output data signal. The third inverter circuit comprises a third set of inverters and a third set of transmission gates.
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