Invention Grant
- Patent Title: Circuit design routing using multi-panel track assignment
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Application No.: US16292012Application Date: 2019-03-04
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Publication No.: US10706201B1Publication Date: 2020-07-07
- Inventor: Yi-Xiao Ding , Mehmet Can Yildiz
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F30/30
- IPC: G06F30/30 ; G06F30/394

Abstract:
Various embodiments provide for circuit design routing using a track assignment based on a plurality of panels (also referred to herein as a multi-panel track assignment). According to some embodiments, a track assignment of a wire within a particular panel is performed based on a primary panel bound or limit and a secondary panel bound or limit. For instance, during a track assignment for a particular wire falling within a particular panel, an embodiment can first attempt to assign the particular wire to a track that falls within panels within the primary panel bound and, if deemed not possible (e.g., due to a DRC, violation or congestion issue), the embodiment can then assign the particular wire to a track that falls within panels within the secondary panel bound.
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