Invention Grant
- Patent Title: Dishing prevention structures and related methods for semiconductor devices
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Application No.: US15914435Application Date: 2018-03-07
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Publication No.: US10707085B2Publication Date: 2020-07-07
- Inventor: Alim Karmous
- Applicant: Infineon Technologies Austria AG
- Applicant Address: AT Villach
- Assignee: Infineon Technologies Austria AG
- Current Assignee: Infineon Technologies Austria AG
- Current Assignee Address: AT Villach
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L21/306
- IPC: H01L21/306 ; H01L21/308 ; H01L21/321 ; H01L21/3105 ; H01L29/73 ; H01L29/861 ; H01L21/762 ; H01L29/66 ; H01L49/02 ; H01L29/786

Abstract:
A method of manufacturing a semiconductor device includes: forming an isolation region comprising a dielectric material on a substrate; forming a recess in the isolation region, wherein a thickness of the isolation region is reduced but greater than zero in the recess; forming a fill layer or layer stack including at least one of a semiconductor or metal on the isolation region and which conforms to the recess; forming a dishing prevention layer or layer stack on the fill layer or layer stack and which conforms to the recess; planarizing the dishing prevention layer or layer stack and the fill layer or layer stack to confine the dishing prevention layer or layer stack and the fill layer or layer stack to the recess, wherein the planarizing stops on the isolation region outside the recess; and forming one or more electrical contacts to the fill layer or layer stack confined to the recess.
Public/Granted literature
- US20190279875A1 Dishing Prevention Structures and Related Methods for Semiconductor Devices Public/Granted day:2019-09-12
Information query
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