Invention Grant
- Patent Title: Electrical connectivity of die to a host substrate
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Application No.: US15817712Application Date: 2017-11-20
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Publication No.: US10707160B2Publication Date: 2020-07-07
- Inventor: Robert T. Carroll
- Applicant: Infineon Technologies Americas Corp.
- Applicant Address: US CA El Segundo
- Assignee: Infineon Technologies Americas Corp.
- Current Assignee: Infineon Technologies Americas Corp.
- Current Assignee Address: US CA El Segundo
- Agency: Armis IP Law, LLC
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/495 ; H01L23/00 ; H01L21/48 ; H01L21/768 ; H01L23/482 ; H01L23/50 ; H01L27/06 ; H01L29/423 ; H02M3/335 ; H01L27/088 ; H02M3/158

Abstract:
According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc.
Public/Granted literature
- US20180076124A1 ELECTRICAL CONNECTIVITY OF DIE TO A HOST SUBSTRATE Public/Granted day:2018-03-15
Information query
IPC分类: