Invention Grant
- Patent Title: 3D stacked integrated circuits having functional blocks configured to provide redundancy sites
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Application No.: US16218901Application Date: 2018-12-13
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Publication No.: US10707197B1Publication Date: 2020-07-07
- Inventor: Tony M. Brewer
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Greenberg Traurig
- Main IPC: H01L25/18
- IPC: H01L25/18 ; H01L23/522 ; H01L27/06 ; H01L27/118 ; G11C29/00 ; H01L25/065 ; H01L23/48 ; G11C29/14 ; G11C29/44 ; H01L25/00 ; G06F11/16 ; G06F11/20

Abstract:
A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.
Information query
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