Invention Grant
- Patent Title: MOSFET with reduced resistance
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Application No.: US14981483Application Date: 2015-12-28
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Publication No.: US10707327B2Publication Date: 2020-07-07
- Inventor: Patrick M. Shea , David N. Okada , Samuel J. Anderson
- Applicant: Great Wall Semiconductor Corporation
- Applicant Address: US AZ Tempe
- Assignee: Great Wall Semiconductor Corporation
- Current Assignee: Great Wall Semiconductor Corporation
- Current Assignee Address: US AZ Tempe
- Agency: Foley & Lardner LLP
- Main IPC: H01L27/118
- IPC: H01L27/118 ; H01L29/66 ; H01L23/485 ; H01L29/78 ; H01L23/00 ; H01L29/417 ; H01L23/495 ; H01L21/56 ; H01L29/10 ; H01L23/31

Abstract:
A semiconductor device includes a semiconductor substrate including a doped region. A metal layer is formed on the doped region. An insulating layer covers the metal layer. The metal layer can serve as a buried metal layer which reduces electrical resistance between electrical charge in the doped region and adjacent contacts. The contacts can extend through the insulating layer between the buried metal layer and overlying metal stripes.
Public/Granted literature
- US20160308015A1 MOSFET with Reduced Resistance Public/Granted day:2016-10-20
Information query
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