Invention Grant
- Patent Title: MOS power transistors in parallel channel configuration
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Application No.: US15708839Application Date: 2017-09-19
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Publication No.: US10707856B2Publication Date: 2020-07-07
- Inventor: Florian Brugger , Christian Djelassi-Tscheck , Alexander Mayer
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Shumaker & Sieffert, P.A.
- Main IPC: H03K17/00
- IPC: H03K17/00 ; H03K17/082 ; H03K17/12 ; H03K17/0812 ; H02H3/087 ; H02H1/00 ; H02H3/05

Abstract:
A circuit comprises a first metal-oxide semiconductor, MOS, power transistor having a first gate terminal, a first drain terminal, and a first source terminal, a second MOS power transistor having a second gate terminal, a second drain terminal, and a second source terminal, and a switch connected in-between the first gate terminal and the second gate terminal and configured to selectively couple the first gate terminal and the second gate terminal.
Public/Granted literature
- US20190089343A1 MOS POWER TRANSISTORS IN PARALLEL CHANNEL CONFIGURATION Public/Granted day:2019-03-21
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