The apparatus (SW) has a plurality of input/output ports (P1, P2, P3, P4, P5) for receiving and transmitting data packets, and comprises a data packets handling circuitry (DPL) arranged to forward data packets between the input/output ports (P1, P2, P3, P4, P5) and an internal apparatus controller (CPL) arranged to control the data packet handling circuitry (DPL); the apparatus controller (CPL) is arranged to store (MEM) at least one state transition table (TT) to be used for controlling the forwarding of data packets by the data packets handling circuitry (DPL); the apparatus controller (CPL) is arranged to use the state transition table (TT) for implementing at least one finite state machine (FSM); the apparatus controller (CPL) is arranged to use the state transition table (TT) for handling separately distinct incoming data packets flows through corresponding distinct instances of finite state machine; the state transition table (TT) corresponds to the combination of a state table (ST), a condition table (CT) and a flow table (FT); the apparatus controller (CPL) is arranged to store (MEM) the state table (ST), the condition table (CT) and the flow table (FT); the apparatus controller (CPL) comprises a condition logic (CL) for calculating conditions stored in the condition table (CT) based on data from the state table (ST) in order to query the flow table (FT).