Invention Grant
- Patent Title: Low cost design for test architecture
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Application No.: US16403580Application Date: 2019-05-05
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Publication No.: US10712388B2Publication Date: 2020-07-14
- Inventor: Chinsong Sul
- Applicant: Chinsong Sul
- Agent Pamela Lau Kee
- Main IPC: G06F30/30
- IPC: G06F30/30 ; G01R31/3183 ; G01R31/317 ; G06F30/33 ; G06F30/3308

Abstract:
The Translation Layer is embedded into each circuit under test (CUT) to modularize test process. The modularized tests are self-contained and performed in isolation. They are composed without consideration of environment constraints. The CUT and its environment constraints can be concurrently be tested in isolation and independently. Interconnections between the CUT and the environment can be tested in the environment constraint test without additional dedicated test logic. The modularized test process allows the test patterns of the environment constraints to be derived from those of the CUT. The resulting test patterns are used to compose the test patterns of a target system. Since the test process is recursive in nature, the modularized test of each constituent subsystem or design core can be performed in isolation in the target system, while the environment constraints and the interconnections are being tested concurrently.
Public/Granted literature
- US20190324083A1 Low Cost Design For Test Architecture Public/Granted day:2019-10-24
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