- Patent Title: High bandwidth soundwire master with multiple primary data lanes
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Application No.: US16012532Application Date: 2018-06-19
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Publication No.: US10713199B2Publication Date: 2020-07-14
- Inventor: Lior Amarilio , Amit Gil , Sharon Graif
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza LLP
- Main IPC: G06F13/364
- IPC: G06F13/364 ; G06F1/08 ; G06F3/16 ; H04R3/00 ; H04R3/12 ; G06F13/42 ; G06F1/12

Abstract:
System, methods and apparatus are described that can improve available bandwidth on a SoundWire bus without increasing the number of pins used by the SoundWire bus. A method performed at a master device coupled to a SoundWire bus includes providing a clock signal by a first master device over a clock line of a SoundWire bus to a first slave device and a second slave device coupled to the SoundWire bus, transmitting first control information from the first master device to the first slave device over a first data line of the SoundWire bus, and transmitting second control information from the first master device to the second slave device over a second data line of the SoundWire bus. The first control information may be different from the second control information and is transmitted concurrently with the second control information.
Public/Granted literature
- US20180373659A1 HIGH BANDWIDTH SOUNDWIRE MASTER WITH MULTIPLE PRIMARY DATA LANES Public/Granted day:2018-12-27
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