Invention Grant
- Patent Title: Integrated circuit design system with automatic timing margin reduction
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Application No.: US16351366Application Date: 2019-03-12
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Publication No.: US10713409B2Publication Date: 2020-07-14
- Inventor: Jeffrey Fredenburg , Muhammad Faisal , David M. Moore , Ramin Shirani , Yu Huang
- Applicant: Movellus Circuits Incorporated
- Applicant Address: US MI Ann Arbor
- Assignee: Movellus Circuits, Inc.
- Current Assignee: Movellus Circuits, Inc.
- Current Assignee Address: US MI Ann Arbor
- Agency: Peninsula Patent Group
- Agent Lance Kreisman
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50 ; G06F30/392 ; G06F30/3312 ; G06F119/12 ; G06F119/18

Abstract:
An integrated circuit (IC) device is disclosed. The IC device includes a global clock source to generate a global clock signal. Multiple local clock sources are employed in the IC device. Each local clock source provides a local clock signal for a partitioned sub-design block in the IC device. Each local clock signal is based on the global clock signal. The IC device includes a clock controller having inputs from the global clock source and the multiple local clock sources. The clock controller (1) measures skew between each local clock source and the global clock source, and (2) generates respective control signals to adjust respective phases of each local clock signal to reduce the measured skew.
Public/Granted literature
- US20190213297A1 INTEGRATED CIRCUIT DESIGN SYSTEM WITH AUTOMATIC TIMING MARGIN REDUCTION Public/Granted day:2019-07-11
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