Invention Grant
- Patent Title: Semiconductor device and semiconductor wafer including a porous layer and method of manufacturing
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Application No.: US16122456Application Date: 2018-09-05
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Publication No.: US10714377B2Publication Date: 2020-07-14
- Inventor: Ingo Muri , Bernhard Goller , Iris Moder , Hans-Joachim Schulze
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Murphy, Bilak & Homiller, PLLC
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@556ec633
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L29/861 ; H01L21/306 ; H01L29/66 ; H01L29/739 ; H01L29/78 ; H01L29/08 ; H01L29/32 ; H01L21/02 ; H01L21/66 ; H01L23/00 ; H01L29/06 ; H01L29/16 ; H01L21/265 ; H01L21/266 ; H01L21/84 ; H01L27/12 ; H01L29/10 ; H01L29/423
Abstract:
A method of manufacturing a semiconductor device includes forming an auxiliary mask including a plurality of mask openings on a main surface of a crystalline semiconductor substrate. A porous structure is formed in the semiconductor substrate. The porous structure includes a porous layer at a distance to the main surface and porous columns that extend from the porous layer into direction of the main surface and that are laterally separated from each other by a non-porous portion. A non-porous device layer is formed on the non-porous portion and on the porous columns.
Public/Granted literature
- US20190074212A1 Semiconductor Device and Semiconductor Wafer Including a Porous Layer and Method of Manufacturing Public/Granted day:2019-03-07
Information query
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