Invention Grant
- Patent Title: Variable gate lengths for vertical transistors
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Application No.: US16455801Application Date: 2019-06-28
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Publication No.: US10714396B2Publication Date: 2020-07-14
- Inventor: Brent A. Anderson , Edward J. Nowak
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Christopher K. McLane; Alexander G. Jochym
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/311 ; H01L21/3213 ; H01L29/66 ; H01L27/088 ; H01L29/423 ; H01L29/49 ; H01L29/78

Abstract:
The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height.
Public/Granted literature
- US20190318965A1 VARIABLE GATE LENGTHS FOR VERTICAL TRANSISTORS Public/Granted day:2019-10-17
Information query
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