Invention Grant
- Patent Title: Method and apparatus of forming high voltage varactor and vertical transistor on a substrate
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Application No.: US16227304Application Date: 2018-12-20
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Publication No.: US10714470B2Publication Date: 2020-07-14
- Inventor: Kangguo Cheng , Ruilong Xie , Tenko Yamashita , Chun-Chen Yeh
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Garg Law Firm, PLLC
- Agent Rakesh Garg; Joseph Petrokaitis
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L27/06 ; H01L29/66 ; H01L21/762 ; H01L29/08 ; H01L21/033 ; H01L29/78 ; H01L29/93 ; H01L21/8234 ; H01L29/786 ; H01L29/51

Abstract:
Fabricating a semiconductor device includes receiving a substrate structure including a substrate. The substrate structure further includes a first bottom source/drain and a first fin formed on a vertical transistor portion of the substrate and a second bottom source/drain and a second fin formed on a varactor portion of the substrate. The substrate structure further includes a bottom spacer formed on the first bottom source/drain of the vertical transistor portion and the second bottom source/drain of the varactor portion. A mask is applied to the portion of the bottom spacer formed on the first bottom source/drain. The portion of the bottom spacer formed on the second bottom source/drain of the varactor portion is removed. The mask is removed from the portion of the bottom spacer formed on the first bottom source/drain. A gate oxide is deposited on the vertical transistor portion and the varactor portion.
Public/Granted literature
- US20190148362A1 METHOD AND APPARATUS OF FORMING HIGH VOLTAGE VARACTOR AND VERTICAL TRANSISTOR ON A SUBSTRATE Public/Granted day:2019-05-16
Information query
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