Invention Grant
- Patent Title: Three-dimensional semiconductor memory devices including through-interconnection structures
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Application No.: US16108294Application Date: 2018-08-22
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Publication No.: US10714495B2Publication Date: 2020-07-14
- Inventor: Kwonsoon Jo , Seo-Goo Kang , Younghwan Son , Kohji Kanamori
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-Do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si, Gyeonggi-Do
- Agency: F. Chau & Associates, LLC
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@457df8ac
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L27/1157 ; H01L23/532 ; G11C7/14 ; G11C7/18 ; H01L27/11573 ; H01L27/11565 ; G11C16/00 ; H01L27/11575 ; G11C5/02

Abstract:
A three-dimensional semiconductor memory device includes a peripheral logic structure including a plurality of peripheral logic circuits disposed on a semiconductor substrate, a horizontal semiconductor layer disposed on the peripheral logic structure, an electrode structure including a plurality of electrodes and insulating layers vertically and alternately stacked on the horizontal semiconductor layer, and a through-interconnection structure penetrating the electrode structure and the horizontal semiconductor layer and including a through-plug connected to the peripheral logic structure. A sidewall of a first insulating layer of the insulating layers is spaced apart from the through-plug by a first distance. A sidewall of a first electrode of the electrodes is spaced apart from the through-plug by a second distance greater than the first distance.
Public/Granted literature
- US20190172838A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES Public/Granted day:2019-06-06
Information query
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