Invention Grant
- Patent Title: Co-integration of bulk and SOI transistors
-
Application No.: US16057466Application Date: 2018-08-07
-
Publication No.: US10714501B2Publication Date: 2020-07-14
- Inventor: Jean-Jacques Fagot , Philippe Boivin , Franck Arnaud
- Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Rousset FR Crolles
- Assignee: STMicroelectronics (Rousset) SAS,STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS,STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Rousset FR Crolles
- Agency: Crowe & Dunlevy
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@24196251
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/762 ; H01L21/84 ; H01L29/808 ; H01L27/06

Abstract:
An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
Public/Granted literature
- US20190057981A1 CO-INTEGRATION OF BULK AND SOI TRANSISTORS Public/Granted day:2019-02-21
Information query
IPC分类: