Invention Grant
- Patent Title: Metal gate process for FinFET device improvement
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Application No.: US16570686Application Date: 2019-09-13
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Publication No.: US10714588B2Publication Date: 2020-07-14
- Inventor: Che-Cheng Chang , Chih-Han Lin , Horng-Huei Tseng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/51
- IPC: H01L29/51 ; H01L21/28 ; H01L29/66 ; H01L29/78 ; H01L21/265 ; H01L21/3115
Abstract:
In a method for manufacturing a semiconductor device, a substrate is provided. A dummy gate is formed on the substrate. A first dielectric layer is formed to peripherally enclose the dummy gate over the substrate. A second dielectric layer is formed to peripherally enclose the first dielectric layer over the substrate. The second dielectric layer and the first dielectric layer are formed from different materials. An implant operation is performed on the first dielectric layer to form a first doped portion in the first dielectric layer. The dummy gate is removed to form a hole in the first dielectric layer. An operation of removing the dummy gate includes removing a portion of the first doped portion to form the hole having a bottom radial opening area and a top radial opening area which is greater than the bottom radial opening area. A metal gate is formed in the hole.
Public/Granted literature
- US20200006513A1 Metal Gate Process for FinFET Device Improvement Public/Granted day:2020-01-02
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