Invention Grant
- Patent Title: Common test board, IP evaluation board, and semiconductor device test method
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Application No.: US16126566Application Date: 2018-09-10
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Publication No.: US10718789B2Publication Date: 2020-07-21
- Inventor: Masato Onda , Seiji Sakurai
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: White & Case LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@1888f29f
- Main IPC: G01R31/26
- IPC: G01R31/26 ; G01R1/04 ; G01R31/3185 ; G01R31/28
Abstract:
According to one embodiment, there is provided a common test board including a socket board, an IP evaluation board, and a common board. To the socket board, a semiconductor device is to be connected. On the IP evaluation board, the socket board is able to be attached. On the common board, the IP evaluation board is able to be attached.
Public/Granted literature
- US20190004088A1 COMMON TEST BOARD, IP EVALUATION BOARD, AND SEMICONDUCTOR DEVICE TEST METHOD Public/Granted day:2019-01-03
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