Invention Grant
- Patent Title: Memory system for controlling nonvolatile memory
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Application No.: US15820516Application Date: 2017-11-22
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Publication No.: US10719393B2Publication Date: 2020-07-21
- Inventor: Shinichi Kanno
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Tokyo
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Tokyo
- Agency: White & Case LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@30f00d22
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F12/1009 ; G06F3/06 ; G11C29/52 ; G06F12/02

Abstract:
According to one embodiment, a memory system copies content of a first logical-to-physical address translation table corresponding to a first region of a nonvolatile memory to a second logical-to-physical address translation table corresponding to a second region of the nonvolatile memory. When receiving a read request specifying a logical address in the second region, the memory system reads a part of the first data from the first region based on the second logical-to-physical address translation table. The memory system detects a block which satisfies a refresh condition from a first group of blocks allocated to the first region, corrects an error of data of the detected block and writes the corrected data back to the detected block.
Public/Granted literature
- US20190004964A1 MEMORY SYSTEM FOR CONTROLLING NONVOLATILE MEMORY Public/Granted day:2019-01-03
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