Invention Grant
- Patent Title: Hardware-based virtual-to-physical address translation for programmable logic masters in a system on chip
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Application No.: US16016349Application Date: 2018-06-22
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Publication No.: US10719452B2Publication Date: 2020-07-21
- Inventor: Ygal Arbel , Sagheer Ahmad , Gaurav Singh
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: G06F12/1027
- IPC: G06F12/1027 ; H03K19/1776
Abstract:
An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.
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Information query
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